Cadence Design Systems (Cadence)

Software : Engineering : Semiconductor

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San Jose, California, United States

NASDAQ: CDNS

Cadence is a pivotal leader in electronic design, building upon more than 30 years of computational software expertise. The company applies its underlying Intelligent System Design strategy to deliver software, hardware and IP that turn design concepts into reality. Cadence customers are the worldโ€™s most innovative companies, delivering extraordinary electronic products from chips to boards to systems for the most dynamic market applications including consumer, hyperscale computing, 5G communications, automotive, aerospace, industrial and health.

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Cadence Strengthens Tensilica Vision and AI Software Partner Ecosystem for Advanced Automotive, Mobile, Consumer and IoT Applications

๐Ÿ“… Date:

๐Ÿ”– Topics: Partnership

๐Ÿข Organizations: Cadence, Kudan, Visionary AI


Cadence Design Systems, Inc. (Nasdaq: CDNS) today announced that it has welcomed Kudan and Visionary.ai to the Tensilica software partner ecosystem, bringing industry-leading simultaneous localization and mapping (SLAM) and AI image signal processor (ISP) solutions to Cadenceยฎ Tensilicaยฎ Vision DSPs and AI platforms. The broad Tensilica Vision and AI software ecosystem includes more than 50 partners developing solutions for these platforms, covering automotive, smartphone apps, IoT, software services, and many other segments.

Kudan is an industry leader in visual odometry and an early implementer of SLAM algorithms. Visionary.aiโ€™s efficient AI-ISP enables customers to implement a camera pipeline with resolutions greater than full HD while operating at over 30fps on the Tensilica NNA110 accelerator.

Read more at Cadence Press Releases

Michigan Electric Boat Propels the Naval Industry with Cadence CFD Tools, Including Fine Marine

Designing Billions of Circuits with Code

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๐Ÿ”– Topics: Electronic Design Automation

๐Ÿญ Vertical: Semiconductor

๐Ÿข Organizations: Cadence, Synopsys


Bringing EDA to silicon helped solve daunting challenges in chip making. A chip is built in layers. Now you have to wire connections in 3-D, taking into consideration layer-to-layer connections called vias.

Read more at Asianometry

AI-Powered Verification

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๐Ÿ”– Topics: Machine Learning

๐Ÿญ Vertical: Semiconductor

๐Ÿข Organizations: Agnisys, Cadence


โ€œWe see AI as a disruptive technology that will in the long run eliminate, and in the near term reduce the need for verification,โ€ says Anupam Bakshi, CEO and founder of Agnisys. โ€œWe have had some early successes in using machine learning to read user specifications in natural language and directly convert them into SystemVerilog Assertions (SVA), UVM testbench code, and C/C++ embedded code for test and verification.โ€

There is nothing worse than spending time and resources to not get the desired result, or for it to take longer than necessary. โ€œIn formal, we have multiple engines, different algorithms that are working on solving any given property at any given time,โ€ says Pete Hardee, director for product management at Cadence. โ€œIn effect, there is an engine race going on. We track that race and see for each property which engine is working. We use reinforcement learning to set the engine parameters in terms of which engines Iโ€™m going to use and how long to run those to get better convergence on the properties that didnโ€™t converge the first time I ran it.โ€

Read more at Semiconductor Engineering

Autonomous Design Automation: How Far Are We?

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โœ๏ธ Author: Frank Schirrmeister

๐Ÿ”– Topics: Generative Design

๐Ÿข Organizations: Cadence


As an industry, we will refine the different levels of Autonomous Design Automation further over the years to come. Eventually, the combination of the different steps of the flow with AI/ML will unlock even further productivity improvements. How long will it be until designers define a function in a higher-level language like SysML and, based on the designerโ€™s requirements, autonomously implement it as a hardware/software system after AI/ML-controlled design-space exploration?

Read more at Semi Engineering

Improving PPA In Complex Designs With AI

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โœ๏ธ Author: John Koon

๐Ÿ”– Topics: Reinforcement Learning, Generative Design

๐Ÿญ Vertical: Semiconductor

๐Ÿข Organizations: Google, Cadence, Synopsys


The goal of chip design always has been to optimize power, performance, and area (PPA), but results can vary greatly even with the best tools and highly experienced engineering teams. AI works best in design when the problem is clearly defined in a way that AI can understand. So an IC designer must first see if there is a problem that can be tied to a systemโ€™s ability to adapt to, learn, and generalize knowledge/rules, and then apply these knowledge/rules to an unfamiliar scenario.

Read more at Semiconductor Engineering

Rodelta Optimizes Pumps for Cavitation-Free, Max-Impact/Min-Consumption Performance with Omnis CFD

How To Measure ML Model Accuracy

๐Ÿ“… Date:

โœ๏ธ Author: Bryon Moyer

๐Ÿ”– Topics: machine learning

๐Ÿข Organizations: Ansys, Brainome, Cadence, Flex Logix, Synopsys, Xilinx


Machine learning (ML) is about making predictions about new data based on old data. The quality of any machine-learning algorithm is ultimately determined by the quality of those predictions.

However, there is no one universal way to measure that quality across all ML applications, and that has broad implications for the value and usefulness of machine learning.

Read more at Semiconductor Engineering

Edge-Inference Architectures Proliferate

๐Ÿ“… Date:

โœ๏ธ Author: Bryon Moyer

๐Ÿ”– Topics: AI, machine learning, edge computing

๐Ÿญ Vertical: Semiconductor

๐Ÿข Organizations: Cadence, Hailo, Google, Flex Logix, BrainChip, Synopsys, GrAI Matter, Deep Vision, Maxim Integrated


What makes one AI system better than another depends on a lot of different factors, including some that arenโ€™t entirely clear.

The new offerings exhibit a wide range of structure, technology, and optimization goals. All must be gentle on power, but some target wired devices while others target battery-powered devices, giving different power/performance targets. While no single architecture is expected to solve every problem, the industry is in a phase of proliferation, not consolidation. It will be a while before the dust settles on the preferred architectures.

Read more at Semiconductor Engineering